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? 2001 mos integrated circuit pd161641 240-output tft-lcd gate driver data sheet document no. s15678ej1v0ds00 (1st edition) date published july 2002 ns cp(k) printed in japan the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the pd161641 is a tft-lcd gate driver. because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a cmos-level input. features ? high breakdown voltage output (v t -v b = 37 v max.) ? 3.0 v cmos level input ? number of output: 240 ordering information part number package pd161641n-xxx tcp (tab package) pd161641p chip remark purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
data sheet s15678ej1v0ds 2 pd161641 1. block diagram sr1 sr2 sr87 mpx sr88 sr89 sr90 sr239 sr240 v ee v ss v cc1 v t stvl o 239 o 240 o 1 o 2 r,/l clk stvr oe2 oe1 v b level shifter o 89 o 90 o 87 o 88 pv ss pv cc1 stvsel oe1sel oe2sel remark /xxx indicates active low si gnal.
data sheet s15678ej1v0ds 3 pd161641 2. pin configuration (pad layout) chip size: 9.4 x 3.5 mm 2 bump size: input (include input side dummy and short-side dummy): 49 x 85 m 2 output (include output side dummy): 35 x 94 m 2 (0,0) no.119 no.122 no.1 no.118 no.123 no.380 no.384 no.381 face up x y 30 m alignment mark 30 m 30 m 30 m 30 m 30 m
data sheet s15678ej1v0ds 4 pd161641 table 2 ? ? ? ? 1. pad layout (1/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] 66 dummy -0.4875 -1.6145 - alignment mark 4.5650 -1.6145 67 dummy -0.5625 -1.6145 68 dummy -0.6375 -1.6145 1 dummy 4.3875 -1.6145 69 dummy -0.7125 -1.6145 2 dummy 4.3125 -1.6145 70 vee -0.7875 -1.6145 3 dummy 4.2375 -1.6145 71 vee -0.8625 -1.6145 4 dummy 4.1625 -1.6145 72 vee -0.9375 -1.6145 5 dummy 4.0875 -1.6145 73 vee -1.0125 -1.6145 6 dummy 4.0125 -1.6145 74 vee -1.0875 -1.6145 7 dummy 3.9375 -1.6145 75 dummy -1.1625 -1.6145 8 dummy 3.8625 -1.6145 76 dummy -1.2375 -1.6145 9 dummy 3.7875 -1.6145 77 vb -1.3125 -1.6145 10 dummy 3.7125 -1.6145 78 vb -1.3875 -1.6145 11 dummy 3.6375 -1.6145 79 vb -1.4625 -1.6145 12 dummy 3.5625 -1.6145 80 vb -1.5375 -1.6145 13 dummy 3.4875 -1.6145 81 vb -1.6125 -1.6145 14 dummy 3.4125 -1.6145 82 dummy -1.6875 -1.6145 15 dummy 3.3375 -1.6145 83 dummy -1.7625 -1.6145 16 dummy 3.2625 -1.6145 84 dummy -1.8375 -1.6145 17 dummy 3.1875 -1.6145 85 stvr -1.9125 -1.6145 18 dummy 3.1125 -1.6145 86 stvr -1.9875 -1.6145 19 pvcc1 3.0375 -1.6145 87 stvr -2.0625 -1.6145 20 oe1sel 2.9625 -1.6145 88 stvr -2.1375 -1.6145 21 oe1sel 2.8875 -1.6145 89 stvr -2.2125 -1.6145 22 oe1sel 2.8125 -1.6145 90 dummy -2.2875 -1.6145 23 oe1sel 2.7375 -1.6145 91 stvl -2.3625 -1.6145 24 oe1sel 2.6625 -1.6145 92 stvl -2.4375 -1.6145 25 pvss 2.5875 -1.6145 93 stvl -2.5125 -1.6145 26 oe2sel 2.5125 -1.6145 94 stvl -2.5875 -1.6145 27 oe2sel 2.4375 -1.6145 95 stvl -2.6625 -1.6145 28 oe2sel 2.3625 -1.6145 96 dummy -2.7375 -1.6145 29 oe2sel 2.2875 -1.6145 97 clk -2.8125 -1.6145 30 oe2sel 2.2125 -1.6145 98 clk -2.8875 -1.6145 31 dummy 2.1375 -1.6145 99 clk -2.9625 -1.6145 32 pvcc1 2.0625 -1.6145 100 clk -3.0375 -1.6145 33 stvsel 1.9875 -1.6145 101 clk -3.1125 -1.6145 34 stvsel 1.9125 -1.6145 102 dummy -3.1875 -1.6145 35 stvsel 1.8375 -1.6145 103 oe1 -3.2625 -1.6145 36 stvsel 1.7625 -1.6145 104 oe1 -3.3375 -1.6145 37 stvsel 1.6875 -1.6145 105 oe1 -3.4125 -1.6145 38 pvss 1.6125 -1.6145 106 oe1 -3.4875 -1.6145 39 r,/l 1.5375 -1.6145 107 oe1 -3.5625 -1.6145 40 r,/l 1.4625 -1.6145 108 dummy -3.6375 -1.6145 41 r,/l 1.3875 -1.6145 109 oe2 -3.7125 -1.6145 42 r,/l 1.3125 -1.6145 110 oe2 -3.7875 -1.6145 43 r,/l 1.2375 -1.6145 111 oe2 -3.8625 -1.6145 44 pvcc1 1.1625 -1.6145 112 oe2 -3.9375 -1.6145 45 dummy 1.0875 -1.6145 113 oe2 -4.0125 -1.6145 46 vt 1.0125 -1.6145 114 dummy -4.0875 -1.6145 47 vt 0.9375 -1.6145 115 dummy -4.1625 -1.6145 48 vt 0.8625 -1.6145 116 dummy -4.2375 -1.6145 49 vt 0.7875 -1.6145 117 dummy -4.3125 -1.6145 50 vt 0.7125 -1.6145 118 dummy -4.3875 -1.6145 51 dummy 0.6375 -1.6145 52 dummy 0 . 5625 - 1 . 6145 ? alignment mark - 4 . 5650 - 1 . 6145 53 vcc1 0.4875 -1.6145 54 vcc1 0.4125 -1.6145 55 vcc1 0.3375 -1.6145 56 vcc1 0.2625 -1.6145 57 vcc1 0.1875 -1.6145 58 dummy 0.1125 -1.6145 59 dummy 0.0375 -1.6145 60 dummy -0.0375 -1.6145 61 vss -0.1125 -1.6145 62 vss -0.1875 -1.6145 63 vss -0.2625 -1.6145 64 vss -0.3375 -1.6145 65 vss - 0 . 4125 - 1 . 6145 gate in p uts 75
data sheet s15678ej1v0ds 5 pd161641 table 2 ? ? ? ? 1. pad layout (2/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] 123 dummy -4.4975 1.6100 189 183 -2.1875 1.6100 124 dummy -4.4625 1.4800 190 182 -2.1525 1.4800 125 dummy -4.4275 1.6100 191 181 -2.1175 1.6100 126 dummy -4.3925 1.4800 192 180 -2.0825 1.4800 127 dummy -4.3575 1.6100 193 179 -2.0475 1.6100 128 dummy -4.3225 1.4800 194 178 -2.0125 1.4800 129 dummy -4.2875 1.6100 195 177 -1.9775 1.6100 130 dummy -4.2525 1.4800 196 176 -1.9425 1.4800 131 dummy -4.2175 1.6100 197 175 -1.9075 1.6100 132 240 -4.1825 1.4800 198 174 -1.8725 1.4800 133 239 -4.1475 1.6100 199 173 -1.8375 1.6100 134 238 -4.1125 1.4800 200 172 -1.8025 1.4800 135 237 -4.0775 1.6100 201 171 -1.7675 1.6100 136 236 -4.0425 1.4800 202 170 -1.7325 1.4800 137 235 -4.0075 1.6100 203 169 -1.6975 1.6100 138 234 -3.9725 1.4800 204 168 -1.6625 1.4800 139 233 -3.9375 1.6100 205 167 -1.6275 1.6100 140 232 -3.9025 1.4800 206 166 -1.5925 1.4800 141 231 -3.8675 1.6100 207 165 -1.5575 1.6100 142 230 -3.8325 1.4800 208 164 -1.5225 1.4800 143 229 -3.7975 1.6100 209 163 -1.4875 1.6100 144 228 -3.7625 1.4800 210 162 -1.4525 1.4800 145 227 -3.7275 1.6100 211 161 -1.4175 1.6100 146 226 -3.6925 1.4800 212 160 -1.3825 1.4800 147 225 -3.6575 1.6100 213 159 -1.3475 1.6100 148 224 -3.6225 1.4800 214 158 -1.3125 1.4800 149 223 -3.5875 1.6100 215 157 -1.2775 1.6100 150 222 -3.5525 1.4800 216 156 -1.2425 1.4800 151 221 -3.5175 1.6100 217 155 -1.2075 1.6100 152 220 -3.4825 1.4800 218 154 -1.1725 1.4800 153 219 -3.4475 1.6100 219 153 -1.1375 1.6100 154 218 -3.4125 1.4800 220 152 -1.1025 1.4800 155 217 -3.3775 1.6100 221 151 -1.0675 1.6100 156 216 -3.3425 1.4800 222 150 -1.0325 1.4800 157 215 -3.3075 1.6100 223 149 -0.9975 1.6100 158 214 -3.2725 1.4800 224 148 -0.9625 1.4800 159 213 -3.2375 1.6100 225 147 -0.9275 1.6100 160 212 -3.2025 1.4800 226 146 -0.8925 1.4800 161 211 -3.1675 1.6100 227 145 -0.8575 1.6100 162 210 -3.1325 1.4800 228 144 -0.8225 1.4800 163 209 -3.0975 1.6100 229 143 -0.7875 1.6100 164 208 -3.0625 1.4800 230 142 -0.7525 1.4800 165 207 -3.0275 1.6100 231 141 -0.7175 1.6100 166 206 -2.9925 1.4800 232 140 -0.6825 1.4800 167 205 -2.9575 1.6100 233 139 -0.6475 1.6100 168 204 -2.9225 1.4800 234 138 -0.6125 1.4800 169 203 -2.8875 1.6100 235 137 -0.5775 1.6100 170 202 -2.8525 1.4800 236 136 -0.5425 1.4800 171 201 -2.8175 1.6100 237 135 -0.5075 1.6100 172 200 -2.7825 1.4800 238 134 -0.4725 1.4800 173 199 -2.7475 1.6100 239 133 -0.4375 1.6100 174 198 -2.7125 1.4800 240 132 -0.4025 1.4800 175 197 -2.6775 1.6100 241 131 -0.3675 1.6100 176 196 -2.6425 1.4800 242 130 -0.3325 1.4800 177 195 -2.6075 1.6100 243 129 -0.2975 1.6100 178 194 -2.5725 1.4800 244 128 -0.2625 1.4800 179 193 -2.5375 1.6100 245 127 -0.2275 1.6100 180 192 -2.5025 1.4800 246 126 -0.1925 1.4800 181 191 -2.4675 1.6100 247 125 -0.1575 1.6100 182 190 -2.4325 1.4800 248 124 -0.1225 1.4800 183 189 -2.3975 1.6100 249 123 -0.0875 1.6100 184 188 -2.3625 1.4800 250 122 -0.0525 1.4800 185 187 -2.3275 1.6100 251 121 -0.0175 1.6100 186 186 -2.2925 1.4800 252 dummy 0.0175 1.4800 187 185 -2.2575 1.6100 253 dummy 0.0525 1.6100 188 184 - 2 . 2225 1 . 4800 254 dummy 0 . 0875 1 . 4800 gate out p uts 35
data sheet s15678ej1v0ds 6 pd161641 table 2 ? ? ? ? 1. pad layout (3/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] 255 dummy 0.1225 1.6100 320 58 2.3975 1.4800 256 dummy 0.1575 1.4800 321 57 2.4325 1.6100 257 dummy 0.1925 1.6100 322 56 2.4675 1.4800 258 120 0.2275 1.4800 323 55 2.5025 1.6100 259 119 0.2625 1.6100 324 54 2.5375 1.4800 260 118 0.2975 1.4800 325 53 2.5725 1.6100 261 117 0.3325 1.6100 326 52 2.6075 1.4800 262 116 0.3675 1.4800 327 51 2.6425 1.6100 263 115 0.4025 1.6100 328 50 2.6775 1.4800 264 114 0.4375 1.4800 329 49 2.7125 1.6100 265 113 0.4725 1.6100 330 48 2.7475 1.4800 266 112 0.5075 1.4800 331 47 2.7825 1.6100 267 111 0.5425 1.6100 332 46 2.8175 1.4800 268 110 0.5775 1.4800 333 45 2.8525 1.6100 269 109 0.6125 1.6100 334 44 2.8875 1.4800 270 108 0.6475 1.4800 335 43 2.9225 1.6100 271 107 0.6825 1.6100 336 42 2.9575 1.4800 272 106 0.7175 1.4800 337 41 2.9925 1.6100 273 105 0.7525 1.6100 338 40 3.0275 1.4800 274 104 0.7875 1.4800 339 39 3.0625 1.6100 275 103 0.8225 1.6100 340 38 3.0975 1.4800 276 102 0.8575 1.4800 341 37 3.1325 1.6100 277 101 0.8925 1.6100 342 36 3.1675 1.4800 278 100 0.9275 1.4800 343 35 3.2025 1.6100 279 99 0.9625 1.6100 344 34 3.2375 1.4800 280 98 0.9975 1.4800 345 33 3.2725 1.6100 281 97 1.0325 1.6100 346 32 3.3075 1.4800 282 96 1.0675 1.4800 347 31 3.3425 1.6100 283 95 1.1025 1.6100 348 30 3.3775 1.4800 284 94 1.1375 1.4800 349 29 3.4125 1.6100 285 93 1.1725 1.6100 350 28 3.4475 1.4800 286 92 1.2075 1.4800 351 27 3.4825 1.6100 287 91 1.2425 1.6100 352 26 3.5175 1.4800 288 90 1.2775 1.4800 353 25 3.5525 1.6100 289 89 1.3125 1.6100 354 24 3.5875 1.4800 290 88 1.3475 1.4800 355 23 3.6225 1.6100 291 87 1.3825 1.6100 356 22 3.6575 1.4800 292 86 1.4175 1.4800 357 21 3.6925 1.6100 293 85 1.4525 1.6100 358 20 3.7275 1.4800 294 84 1.4875 1.4800 359 19 3.7625 1.6100 295 83 1.5225 1.6100 360 18 3.7975 1.4800 296 82 1.5575 1.4800 361 17 3.8325 1.6100 297 81 1.5925 1.6100 362 16 3.8675 1.4800 298 80 1.6275 1.4800 363 15 3.9025 1.6100 299 79 1.6625 1.6100 364 14 3.9375 1.4800 300 78 1.6975 1.4800 365 13 3.9725 1.6100 301 77 1.7325 1.6100 366 12 4.0075 1.4800 302 76 1.7675 1.4800 367 11 4.0425 1.6100 303 75 1.8025 1.6100 368 10 4.0775 1.4800 304 74 1.8375 1.4800 369 9 4.1125 1.6100 305 73 1.8725 1.6100 370 8 4.1475 1.4800 306 72 1.9075 1.4800 371 7 4.1825 1.6100 307 71 1.9425 1.6100 372 6 4.2175 1.4800 308 70 1.9775 1.4800 373 5 4.2525 1.6100 309 69 2.0125 1.6100 374 4 4.2875 1.4800 310 68 2.0475 1.4800 375 3 4.3225 1.6100 311 67 2.0825 1.6100 376 2 4.3575 1.4800 312 66 2.1175 1.4800 377 1 4.3925 1.6100 313 65 2.1525 1.6100 378 dummy 4.4275 1.4800 314 64 2.1875 1.4800 379 dummy 4.4625 1.6100 315 63 2 . 2225 1 . 6100 380 dummy 4 . 4975 1 . 4800 316 62 2.2575 1.4800 317 61 2.2925 1.6100 318 60 2.3275 1.4800 319 59 2 . 3625 1 . 6100 gate out p uts 35
data sheet s15678ej1v0ds 7 pd161641 table 2 ? ? ? ? 1. pad layout (4/4) pad no. pad name x [mm] y [mm] pad no. pad name x [mm] y [mm] 381 dummy 4.5825 1.1250 119 dummy -4.5825 -1.1250 382 dummy 4.5825 0.3750 120 dummy -4.5825 -0.3750 383 dummy 4.5825 -0.3750 121 dummy -4.5825 0.3750 384 dummy 4 . 5825 - 1 . 1250 122 dummy - 4 . 5825 1 . 1250 gate ri g ht 75
data sheet s15678ej1v0ds 8 pd161641 3. pin functions (1/2) symbol pin name pad no. i/o function o 1 to o 240 driver output 132 to 251, 258 to 377 output scan signal output pins that drive the gate electrode of a tft- lcd. the status of each output pin changes in synchronization with the rising edge of shift clock. the output voltage of the driver is v t -v b . stvr, stvl start pulse input/output 85 to 89, 91 to 95 i/o input/output pin of the internal shift register. read of start pulse signal is set at rising edge of shift clock, and outputs a scanning signal from a driver output pin. in addition, the effective level of a stvr/stvl pin is determined by setup of stvsel pin. moreover, an input/output level is v cc1 -v ss (logic level). stvsel = l: start pulse is set to low level by the 240th falling edge of shift clock, and is set to a high level by the 241st falling edge. stvsel start pulse input effective level selection 33 to 37 input the effective level of the start pulse signal inputted into stvr/stvl is selected. stvsel = l: low level stvsel = h: high level clk shift clock input 97 to 101 input shift clock input for the internal shift register. the contents of internal shift register is shifted at the rising edge of clk. connect to gclk pin of source driver. r,/l shift direction switching input 39 to 43 input shift direction switching input pin of the internal shift register. r,/l = h (right shift): stvr o 1 o 2 o 239 o 240 stvl r,/l = l (left shift): stvl o 240 o 239 o 2 o 1 stvr oe1 enable input 103 to 107 input input of the level selected by oe1sel fixes a driver output to a low level (input of a low level fixes driver output to low level at the time of oe1sel = l). however, shift register is not cleared. moreover, output enable operation is asynchronous on a clock. connect with goe1 pin of sauce driver. oe1sel oe1 effective level selection 20 to 24 input this pin selects effective level of oe1 pin. oe1sel = l: low level oe1sel = h: high level oe2 enable input 109 to 113 input input of the level selected by oe2sel fixes a driver output to a high level (input of a low level fixes driver output to high level at the time of oe2sel = l). however, shift register is not cleared. moreover, output enable operation is asynchronous on a clock. connect with goe2 pin of sauce driver. oe2sel oe2 effective level selection 26 to 30 input this pin selects effective level of oe2 pin. oe2sel = l: low level oe2sel = h: high level
data sheet s15678ej1v0ds 9 pd161641 (2/2) symbol name pad no. i/o function v t positive power supply for driver 48 to 50 ? positive power supply for level shifter and output buffer. positive power supply for liquid crystal. v ee negative power supply for logic 70 to 74 ? negative power supply for level shifter. v b negative power supply for driver 77 to 81 ? negative power supply for output buffer. negative power supply for liquid crystal. v cc1 positive power supply for logic 53 to 57 ? positive power supply for logic circuit. v ss ground 61 to 65 ? connect to the system ground. pv cc1 pull-up power supply 19, 32, 44 ? pull-up power supply for mode setting pins (r,/l, stvsel, oe1sel, oe2sel). pv ss pull-down power supply 25, 38 ? pull-down power supply for mode setting pins (r,/l, stvsel, oe1sel, oe2sel). 4. mode description output mode selection r,/l stvr stvl scan direction h input output 1 240 l output input 240 1 remark h: v cc1 , l: v ss
data sheet s15678ej1v0ds 10 pd161641 5. timing chart the timing chart in each conditions is shown as follows. r,/l = h, stvsel = l, oe1sel = l, oe2sel = l clk oe1 oe2 stvr o 1 o 2 o 3 o 240 stvl (o 1 ) (o 2 ) (o 3 ) 1 23 4 240 241 242 243 244 245 r,/l = l, stvsel = h, oe1sel = h, oe2sel = h clk oe1 oe2 stvl o 240 o 239 o 238 o 1 stvr (o 240 ) (o 239 ) (o 238 ) 240 241 242 243 1 2 3 4 245 244
data sheet s15678ej1v0ds 11 pd161641 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit supply voltage v t ?0.5 to +23 v supply voltage v cc1 ?0.5 to +7.0 v supply voltage v t -v ee ?0.5 to +40 v supply voltage v ee v t ? 38 to +0.5 v supply voltage v b v ee +0.5 to +0.5 v input voltage note v i ? 0.5 to v cc1 +0.5 v operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 55 to +150 c note r,/l, clk, stvr, stvl, oe1, oe2, stvsel, oe1sel, oe2sel caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = ?40 to +85 c, v ss = 0 v) parameter symbol min. typ. max. unit supply voltage v t 8.5 15 20.5 v supply voltage v ee ?16.5 ?15 ?13.5 v supply voltage v b v ee +1 v ee +12 v supply voltage v t -v ee 22 37 v supply voltage v cc1 2.5 2.7 3.6 v input voltage note v i 0v cc1 v note r,/l, clk, stvr, stvl, oe1, oe2, stvsel, oe1sel, oe2sel
data sheet s15678ej1v0ds 12 pd161641 electrical characteristics (t a = ? ? ? ? 40 to +85 c, v cc1 = 2.5 to 3.6 v, v t = 15 v, v ee = ? ? ? ? 15 v, v b = ? ? ? ? 11 v, v ss = 0 v) parameter symbol condition min. typ. max. unit high level input voltage v ih1 0.8 v cc1 v cc1 v low level input voltage v il1 r,/l, clk, stvr, stvl, oe1, oe2, stvsel , oe1sel , oe2sel 00.2 v cc1 v high level output voltage v oh stvr, stvl, i oh = ?40 av cc1 ? 0.4 v cc1 v low level output voltage v ol stvr, stvl, i oh = +40 a0 0.4v output on resistance r on1 o 1 to o 240 1.0 k ? input current i i1 logic input pin 1.0 a dynamic current 1 i cc1 v cc1 , note 200 a dynamic current 2 i t v t , note 100 a dynamic current 3 i ee v ee , note 100 a static current note i ss v cc1 , v t in stand-by mode 10 a note f clk = 45.5 khz, output no load switching characteristics (t a = ? ? ? ? 40 to +85 c, v cc1 = 2.5 to 3.6 v, v t = 15 v, v ee = ? ? ? ? 15 v, v b = ? ? ? ? 11 v, v ss = 0 v) parameter symbol condition min. typ. max. unit t phl1 800 ns cascade output delay time t plh1 c l = 20 pf, clk stvl (stvr) 800 ns t phl2 500 ns driver output delay time 1 t plh2 c l = 300 pf, clk o n 500 ns t phl3 500 ns driver output delay time2 t plh3 c l = 300 pf, oe1 on 500 ns t phl4 500 ns driver output delay time 3 t plh4 c l = 300 pf, oe2 on 500 ns output rise time t tlh 800 ns output fall time t thl c l = 300 pf 800 ns input capacitance c i t a = 25 c15pf clock frequency f clk when connected in cascade 500 khz timing requirement (t a = ? ? ? ? 40 to +85 c, v cc1 = 2.5 to 3.6 v, v t = 15 v, v ee = ? ? ? ? 15 v, v b = ? ? ? ? 11 v, v ss = 0 v) parameter symbol condition min. typ. max. unit clock pulse high period pw clk(h) 500 ns clock pulse low period pw clk(l) 500 ns enable pulse high period pw oe oe1, oe2 1 s data setup time t setup stvr (stvl) clk 200 ns data hold time t hold clk stvr (stvl) 200 ns remark the rise and fall times of logic input must be t r = t f = 20 ns (10 to 90%)
data sheet s15678ej1v0ds 13 pd161641 switching characteristics waveform (r,/l = h, stvsel = l, oe1sel = l, oe2sel = l) clk ( ): r,/l = l v dd v ss stvr (stvl) v dd v ss stvl (stvr) v dd v ss oe1 v dd v ss on v gg v ee 1/f clk pw clk(h) pw clk(l) 50% 50% 50% 50% t setup t hold 50% 50% t plh1 t phl1 50% 50% t plh2 t tlh t phl2 t thl 90% 90% 10% 10% pw oe 50% 50% t phl3 t plh3 10% 90% o n v gg v ee oe2 v dd v ss on v gg v ee pw oe 50% 50% t plh4 t phl4 90% 10%
data sheet s15678ej1v0ds 14 pd161641 [memo]
data sheet s15678ej1v0ds 15 pd161641 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd161641 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) m8e 00. 4 the information in this document is current as of july 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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